The present invention generally relates to master-slave flip-flop circuits, and more particularly to a master-slave flip-flop circuit made up of a master part and a slave part.
Conventionally, there exists a master-slave flip-flop circuit which is made up of a master part provided in a first stage and a slave part provided in a latter stage and uses a single phase clock signal by inverting it. Because no clock skew occurs in this flip-flop circuit, no racing phenomenon will occur even when such flip-flop circuits are connected in a plurality of stages. Hence, such flip-flop circuits are often used in a semiconductor integrated circuit.
Recently, with an increase of operation speeds of systems, there are demands for a master-slave flip-flop circuit capable of carrying out a high-speed operation.
FIG. 1 generally shows a conventional master-slave flip-flop circuit. A data signal Din shown in FIG. 2(A) is applied to a terminal 10 and is supplied to a data input terminal D of a master part 11. A clock signal CK shown in FIG. 2(B) is applied to a terminal 12 and is supplied to a clock input terminal C of the master part 11 and to a clock input terminal C of a slave part 13.
The master part 11 enters the data signal Din when the level of the clock signal CK falls to a low level and outputs from an output terminal Q a data signal shown in FIG. 2(C) after a time tpd1 from the fall in the clock signal CK. A data signal which is inverted is output from an output terminal Q of the master part 11. The time tpd1 is a propagation delay time of the master part 11.
The slave part 13 enters the output signals from the output terminals Q and Q of the master part 11 when the level of the clock signal CK rises to a high level and outputs from an output terminal X a data signal shown in FIG. 2(D) after a time tpd2 from the rise in the clock signal. A data signal which is inverted is output from an output terminal X of the slave part 13. The time tpd2 is a propagation delay time of the slave part 13. The output signals of the slave part 13 from the terminals X and X are respectively obtained through output terminals 14 and 15.
In a gate array system semiconductor device, the master part 11 and the slave part 13 are constituted by identical basic cells. Generally, a logic amplitude which is a potential difference between a voltage which describes a value "0" and a voltage which describes a value "1" is set to the same value for the master part 11 and the slave part 13. In addition, the logic amplitude must be set to a sufficiently large value so as to take into account a noise margin of a circuit which is provided in a stage subsequent to the master-slave flip-flop circuit.
However, the times tpd1 and tpd2 become large when the logic amplitude is large and the operation speed of the master-slave flip-flop circuit becomes slow. For this reason, when the data signal Din and the clock signal CK respectively shown in FIGS. 2(E) and 2(F) have high frequencies and a low-level period of the clock signal CK is shorter than the time tpd1, the clock signal CK rises to the high level before the data signal D1 which is sampled by the master part 11 is transmitted to the slave part 13. In this case, the slave part 13 samples the data signal D0 again as may be seen from FIGS. 2(G) and 2(H), thereby resulting in an erroneous operation of the master-slave flip-flop circuit.
On the other hand, the master-slave flip-flop circuit is used in various digital circuits and is used in a form of an integrated circuit to build a system, and there is a need to set and reset signals within the master-slave flip-flop circuit. The signals within the master-slave flip-flop circuit are set and reset when initializing the master-slave flip-flop circuit after building the system or set and reset with an arbitrary timing. Hence, the master-slave flip-flop circuit used in such a system is provided with set and reset functions.
FIG. 3 shows an example of a conventional master-slave flip-flop circuit employing series gate type emitter coupled logic (ECL) circuits and having set and reset functions. The series gate type circuit refers to a circuit in which differential transistor pairs are connected in series in a plurality of stages between voltage sources V.sub.EE and GND.
In FIG. 3, the master-slave flip-flop circuit is made up of a master circuit MST and a slave circuit SLV. The master circuit MST is arranged at an input stage of the master-slave flip-flop circuit and temporarily latches an input logic signal. The master circuit MST also transmits the input logic signal to the slave circuit SLV which is arranged at an output stage so as to output signals through output terminals X and X of the slave circuit SLV. In FIG. 3, Vref1 and Vref2 denote reference voltage signals.
Voltage levels at various parts of the master circuit MST are set so that the master circuit MST operates responsive small amplitude logic signals and carries out a high-speed operation. For example, the small amplitude logic signals indicate a high level when the voltage is -0.9 V and indicate a low level when the voltage is -1.8 V.
Next, a description will be given of a latch operation of the master-slave flip-flop circuit. When the clock signal CK applied to the terminal 12 has a low level and the data signal Din is applied to a base of a transistor T4 through the terminal 10, the transistor T4 turns ON when the logic level of the data signal Din is high and the signal level of the data signal Din is higher than that of the reference voltage signal Vref1. As a result, a current path is formed from the voltage source GND, a level shift resistor r1, a voltage dividing resistor r2, the transistor T4, a transistor T10, a transistor T12, and the voltage source V.sub.EE. The voltage dividing resistor r2 determines the signal amplitude of the circuit.
In this state, a signal level at a node N1 which connects the voltage dividing resistor r2 and a collector of the transistor T4 is low. On the other hand, a signal level at a node N2 which connects a voltage dividing resistor r3 and a collector of a transistor T5 is high. Accordingly, an output transistor T15 transmits a high level, a signal level at a base of a latch transistor T9 becomes high, and the latch transistor T9 turns ON. When the clock signal CK undergoes a transition to a high level in this state, a transistor T11 turns ON. As a result, a current path is formed from the voltage source GND, the level shift resistor r1, the voltage dividing resistor r2, the latch transistor T9, the transistor T11, the transistor T12, and the voltage source V.sub.EE. By the formation of this current path, the high level of the data signal Din is latched and this high level is held thereafter regardless of the existence of the data signal Din.
Next, a description will be given of the reset operation of the master-slave flip-flop circuit. When resetting the high level signal which is held as described above, a high-level reset signal S.sub.R is applied to a terminal 17. Transistors T7 and T11 are forcibly turned ON responsive to the high-level reset signal S.sub.R. As a result, a current path is formed from the voltage source GND, the level shift resistor r1, the voltage dividing resistor r3, the transistor T7, the transistor T11, the transistor T12, and the voltage source V.sub.EE. Thus, the latched high-level signal, that is, the logic level at the node N2 between the voltage dividing resistor r3 and the transistor T5, is inverted from the high level to the low level. Consequently, the output transistor T15 transmits a low level, and the transistor T9 turns OFF. On the other hand, an output transistor T14 transmits a high level, and a transistor T6 turns ON to maintain the reset state. The reset operation is completed in this manner.
Therefore, in order to reset the master-slave flip-flop circuit, a voltage V.sub.H of the reset signal S.sub.R, that is, a base voltage of the transistor T7, must be set higher than a base voltage of the latch transistor T9. The reset voltage V.sub.H must thus satisfy the following relationship (1), where r1 denotes a resistance of the level shift resistor r1, I.sub.CS denotes a current source current, V.sub.BE(T15) denotes a base-emitter voltage of the output transistor T15, I.sub.1 denotes a current flowing through the output transistor T15, and r5 denotes a resistance of an adjusting resistor r5. EQU V.sub.H &gt;-(r1.I.sub.CS +V.sub.BE(T15) +I.sub.1.r5) (1)
As may be seen from the relationship (1), an emitter voltage of the output transistor T15 needs to be set lower than the reset voltage V.sub.H in order to set the base voltage of the transistor T9 to a low value, and this may be achieved by adding a voltage drop Vr5 of an adjusting resistor r5 to a voltage drop Vr1 (=r1.I.sub.CS) of the level shift resistor r1 and the base-emitter voltage V.sub.BE(T15) of the output transistor T15. Hence, the voltage adjustment can be made depending on a resistance of the adjusting resistor r4.
FIG. 4 shows a relationship of the high and low levels of the reset signal S.sub.R and the high and low levels at Q-output and Q-output terminals.
A set operation can be carried out similarly to the reset operation in response to a set signal S.sub.S which is applied to a terminal 18, and a description thereof will be omitted.
As described before, the master-slave flip-flop circuit shown in FIG. 3 is designed to carry out a high-speed operation responsive to small amplitude logic signals. However, the problem of this master-slave flip-flop circuit is that the high-speed operation is restricted by the provision of the adjusting resistor r4 at the output stage of the circuit. In other words, a delay is introduced to the rise and fall of the signal by the adjusting resistor r5 (or r4) which is connected in series to an emitter of the output transistor T15 (or T14). But when this adjusting resistor r5 (or r4) is omitted, there is a problem in that the set and reset operations of the master-slave flip-flop circuit can no longer be carried out satisfactorily.